Design and Performance Evaluation of a Pulsed-Latch-Based Shift Register for Low-Power Applications

Abstract

Shift registers dominate the sequential-logic footprint of modern SoCs, and the storage elements they contain are a leading contributor to both silicon area and clock-network power. Conventional master–slave flip-flop (MSFF) shift registers waste power because every bit toggles a locally distributed clock and carries a redundant latch stage. This paper presents the design and performance evaluation of a shift register built from pulsed latches driven by a shared pulse generator and a set of non-overlapping, delayed pulsed-clock phases. Replacing each MSFF with a single latch removes half of the storage transistors, while the multi-phase pulsed clock resolves the race-through (data-duplication) problem that normally prevents cascaded latches from being used as a register. The design is organised into small sub-registers with temporary storage latches so that only a few pulsed-clock lines are required irrespective of register length. Using a transistor-level implementation in a 45 nm CMOS flow at 1.0 V, the proposed 128- bit register is evaluated for power, propagation delay, power–delay product (PDP), leakage and transistor count against five reference designs. The representative simulation results reported here indicate roughly 45–52 % lower average power, a 40–% lower PDP and a 30– % smaller transistor budget relative to an MSFF baseline, with competitive delay. The numerical values are illustrative and should be reproduced with the reader's own SPICE decks.