DR.RAVI BOLIMERA; K. SHIVA PRASANNA; RANGA DEEPSHIKA; SHANIGARAPU SAIKIRAN; SAPPIDI MALLIKARJUN REDDY. AREA EFFICIENT UART DESIGN USING VERILOG HDL. International Journal of Data Science and IoT Management System, [S. l.], v. 4, n. 4, p. 351–355, 2025. DOI: 10.64751/ijdim.2025.v4.n4.pp351-355. Disponível em: https://ijdim.com/journal/index.php/ijdim/article/view/198. Acesso em: 6 jul. 2026.