AREA EFFICIENT UART DESIGN USING VERILOG HDL

Abstract

With the rapid growth of Integrated Circuits (ICs) technology, the complexity of the circuits has also increased. As a result, the complexity of the circuit demands self-testability in hardware to mitigate the product failure. Built-in-self-test (BIST) is such a technique which can meet the demand of self-testability with an effective solution over costly circuit testing system. This paper represents designing and implementation of a Universal Asynchronous Receiver Transmitter (UART) with self-testing ability. In order to attain compact, stable and reliable data transmission, the UART is designed with Verilog HDL language and synthesized on Spartan2 FPGA. Here, the Baud Rate of the UART is 4 Mbps. This UART also utilizes the RS-422 standard.