DESIGN OF LOW POWER SRAM IN 45nm CMOS TECHNOLOGY

Abstract

SRAM is designed to provide an interface with CPU and to replace DRAMs in systems that require very low power consumption. Low power SRAM design is crucial since it takes a large fraction of total power and die area in high performance processors. A SRAM cell must meet the requirements for the operation in submicron/nano ranges. The scaling of CMOS technology has significant impacts on SRAM cell – random fluctuation of electrical characteristics and substantial leakage current. The random fluctuation of electrical property causes the SRAM cell to have huge mismatch in transistor threshold voltage. Consequently, the static noise margin (Read Margin) and the write margin are degraded dramatically. The SRAM cell tends to be unstable and the low power supply operation becomes hard to achieve.A 6T SRAM cell at 45 nm feature size in CMOS is proposed to accomplish low power memory operation. SRAM (Static Random Access Memory) is widely used for high-speed access in systems requiring close integration with the CPU, and it increasingly replaces DRAM in applications where ultra-low power consumption is critical.