HARNESSING MAJORITY-BASED APPROXIMATION FOR HIGHPERFORMANCE ADDER DESIGN

Abstract

Approximate computing has emerged as a promising paradigm to enhance the efficiency of digital circuits, particularly in error-tolerant applications such as image processing, machine learning, and multimedia systems. Among various arithmetic components, adders are critical due to their frequent use in arithmetic and logic units. This paper investigates the design and performance of majoritybased approximate adders (MBAAs), leveraging majority logic to balance the trade-off between computational accuracy, delay, and power consumption. Unlike conventional approximate adders that often rely on truncation or bit modification, MBAAs utilize majority gates to simplify carry computation while reducing complexity. Experimental analysis demonstrates that MBAAs achieve significant energy savings with minimal accuracy degradation, making them well-suited for resourceconstrained and high-performance computing platforms