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Dr.Ravi Bolimera; Mrs. K. Thrisandhya; Rajulapati. Pavan Kumar; Patha. Vimal Koushik; Shagaanti. Sandeep. DESIGN OF LOW POWER SRAM IN 45nm CMOS TECHNOLOGY. Int. J. Data. Sci. IoT. Manag. Syst. 2025, 4 (4), 43-45. https://doi.org/10.64751/ijdim.2025.v4.n4.pp43-45.