Design and Implementation of a softcore Risc-V RV32-IM, Dual Core Processor on a FPGA

Abstract

For applications involving systems-on-chips and the Internet of Things, the RISC-V ISA is rising to the top of the list of instruction sets. RISC-V offers a scalable solution suitable for a wide range of devices, from simple embedded systems to high-performance systems. Its design centers around simplicity, enabling easy implementation, verification, and customization, thus in this paper, the Softcore processor RV32-IM, Dual Core with in-order superscalar is designed and implemented onto FPGA, As Dual-core processing which has a significant pivotal advancement in computer architecture, introducing heightened performance and independent multitasking prowess compared to their single-core predecessors. By integrating two autonomous processing units within a solitary chip, dual-core processors empower simultaneous execution of multiple tasks, thereby enhancing system responsiveness and operational efficiency. The softcore design of an open-source RISC-V processor utilizing contemporary hardware design methodologies is covered in this paper, along with details on how the softcore design was implemented on an FPGA using Xilinx Vivado software tool which later with Vitis IDE can be used to implement applications, as soft-core processors on FPGAs are often preferred as an alternative to ASICs due to their flexibility, shorter development cycles.