LOW-OVERHEAD DMC DESIGN INSIGHTS FOR ROBUST MEMORY RELIABILITY UNDER MULTIPLE CELL UPSETS

Abstract

As semiconductor technology scales down to nanometer nodes, memory circuits become increasingly vulnerable to soft errors caused by radiation-induced effects such as single event upsets (SEUs) and multiple cell upsets (MCUs). Conventional error correction codes (ECCs) can handle single-bit upsets but often incur high area and power overheads when extended to correct MCUs. To address this challenge, this paper explores low-overhead Double Modular Code (DMC) design for improving memory reliability under MCU conditions. The proposed DMC-based architecture reduces redundancy while maintaining high fault tolerance and ensuring error detection with minimal hardware overhead. Unlike traditional ECC methods, the DMC approach provides scalability and efficiency for modern nano-scaled memory systems. Through simulation and hardware prototype validation, the proposed DMC demonstrates significant improvements in reliability with lower delay and power consumption compared to Hamming and BCH codes, making it highly suitable for mission-critical applications such as aerospace, automotive electronics, and high-performance computing