OPTIMIZED 16NM FULL ADDER CIRCUIT: MUX-BASED HIGHSPEED AND LOW-ENERGY ARCHITECTURE

Abstract

The demand for energy-efficient and high-performance arithmetic circuits has become increasingly critical in nanometer-scale technologies. Among these, the full adder is a fundamental building block used in arithmetic logic units (ALUs), digital signal processors (DSPs), and microprocessors. This paper presents an optimized full adder design using a multiplexer (MUX)-based architecture implemented in 16nm technology. The proposed design emphasizes low power consumption, reduced transistor count, and high switching speed, which are crucial for portable and high-performance computing devices. By leveraging the advantages of MUX logic, the architecture achieves minimized propagation delay, reduced leakage power, and enhanced robustness against process variations. Simulation results validate the effectiveness of the proposed design, showing superior performance in terms of power-delay product (PDP) compared to conventional CMOS and hybrid full adder designs.