LOW-LATENCY ASIC ARCHITECTURE FOR RECURSIVE KARATSUBA MULTIPLICATION EMPLOYING AN EFFICIENT SQRT CARRY SELECT ADDER

Abstract

Computation intensive applications such as DSP, image processing, floating point processors and communication technologies today require efficient binary multiplication which usually is the most power and time-consuming block. This paper proposes an efficient design for unsigned binary multiplication to reduce delay. A 16×16-bit multiplier has been designed which is based on Vedic Karatsuba algorithm using reversible logic. It is optimized using adaptive and recursive approach combined with square-root- carry-select-adder. The designs have been coded in Verilog, synthesized in Xilinx ISE. Index Terms—Square Root Carry Select Adder, reversible logic, Karatsuba Multiplier, Recursive Adaptive Karatsuba Algorithm