HDL BASED DESIGN FOR 32 BIT RIPPLE CARRY ADDER FOR DIGITAL DESIGN

Abstract

The ripple carry adder (RCA) is the most basic method for implementing a summing operation in CMOS-based electronics. A half-adder, which is perhaps the most basic integration circuit, was recently proposed by the scientific discipline, which studies data processing via spin waves and the quanta magnons. To facilitate the design and Modeling of gates and circuits of any complexity, we provide a computation model for the basic blocks. We illustrate its operation using a 32-bit basic RCA as an example. It is demonstrated that to equalize the magnon frequencies between the half-adders, the RCA necessitates the use of extra regenerators based on direction couplers with integrated amplifiers. Electronic circuits on a big scale are benchmarked. When considering all necessary amplifiers as well as the electrical power usage of a 30 nm-based 32-bit adder can be as modest as 961 per execution